{"id":8798,"date":"2026-04-02T11:41:33","date_gmt":"2026-04-02T03:41:33","guid":{"rendered":"https:\/\/www.sic-wafers.com\/?p=8798"},"modified":"2026-04-02T11:41:44","modified_gmt":"2026-04-02T03:41:44","slug":"how-many-skylake-chips-can-be-produced-on-a-300mm-wafer","status":"publish","type":"post","link":"https:\/\/www.sic-wafers.com\/vi\/how-many-skylake-chips-can-be-produced-on-a-300mm-wafer\/","title":{"rendered":"M\u1ed9t t\u1ea5m wafer 300mm c\u00f3 th\u1ec3 s\u1ea3n xu\u1ea5t \u0111\u01b0\u1ee3c bao nhi\u00eau chip Skylake?"},"content":{"rendered":"
<\/div>\n

Qu\u00e1 tr\u00ecnh s\u1ea3n xu\u1ea5t c\u00e1c vi x\u1eed l\u00fd hi\u1ec7n \u0111\u1ea1i, ch\u1eb3ng h\u1ea1n nh\u01b0 d\u00f2ng Skylake c\u1ee7a Intel, b\u1eaft \u0111\u1ea7u t\u1eeb nh\u1eefng t\u1ea5m wafer silicon c\u1ee1 l\u1edbn. Vi\u1ec7c n\u1eafm r\u00f5 m\u1ed9t t\u1ea5m wafer c\u00f3 th\u1ec3 cho ra bao nhi\u00eau chip l\u00e0 \u0111i\u1ec1u v\u00f4 c\u00f9ng quan tr\u1ecdng \u0111\u1ed1i v\u1edbi c\u00e1c nh\u00e0 s\u1ea3n xu\u1ea5t b\u00e1n d\u1eabn, nh\u00e0 thi\u1ebft k\u1ebf ph\u1ea7n c\u1ee9ng v\u00e0 c\u00e1c nh\u00e0 ph\u00e2n t\u00edch ng\u00e0nh. Trong b\u00e0i vi\u1ebft n\u00e0y, ch\u00fang ta s\u1ebd t\u00ecm hi\u1ec3u c\u00e1c y\u1ebfu t\u1ed1 quy\u1ebft \u0111\u1ecbnh s\u1ed1 l\u01b0\u1ee3ng chip Skylake \u0111\u01b0\u1ee3c s\u1ea3n xu\u1ea5t t\u1eeb m\u1ed9t t\u1ea5m wafer ti\u00eau chu\u1ea9n 300mm (12 inch) t\u1ea5m silicon<\/a>, \u00e1p d\u1ee5ng c\u00e1c ph\u01b0\u01a1ng ph\u00e1p hay nh\u1ea5t trong ng\u00e0nh.<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

1. Gi\u1edbi thi\u1ec7u v\u1ec1 ki\u1ebfn tr\u00fac Skylake<\/h2>\n\n\n\n

Skylake l\u00e0 ki\u1ebfn tr\u00fac vi x\u1eed l\u00fd Core th\u1ebf h\u1ec7 th\u1ee9 6 c\u1ee7a Intel, ra m\u1eaft v\u00e0o n\u0103m 2015. Ki\u1ebfn tr\u00fac n\u00e0y \u0111\u01b0\u1ee3c s\u1ea3n xu\u1ea5t d\u1ef1a tr\u00ean c\u00f4ng ngh\u1ec7 FinFET 14nm, h\u1ed7 tr\u1ee3 nhi\u1ec1u nh\u00e2n x\u1eed l\u00fd, c\u00f4ng ngh\u1ec7 Hyper-Threading v\u00e0 \u0111\u1ed3 h\u1ecda t\u00edch h\u1ee3p. T\u00f9y thu\u1ed9c v\u00e0o t\u1eebng m\u1eabu, b\u1ed9 vi x\u1eed l\u00fd Skylake c\u00f3 th\u1ec3 dao \u0111\u1ed9ng t\u1eeb chip di \u0111\u1ed9ng hai nh\u00e2n \u0111\u1ebfn CPU m\u00e1y t\u00ednh \u0111\u1ec3 b\u00e0n b\u1ed1n nh\u00e2n ho\u1eb7c s\u00e1u nh\u00e2n, v\u1edbi k\u00edch th\u01b0\u1edbc die th\u01b0\u1eddng n\u1eb1m trong kho\u1ea3ng t\u1eeb 122 mm\u00b2 \u0111\u1ebfn 151 mm\u00b2.<\/p>\n\n\n\n

K\u00edch th\u01b0\u1edbc khu\u00f4n c\u1ee7a m\u1ed9t con chip l\u00e0 y\u1ebfu t\u1ed1 quan tr\u1ecdng v\u00ec n\u00f3 \u1ea3nh h\u01b0\u1edfng tr\u1ef1c ti\u1ebfp \u0111\u1ebfn s\u1ed1 l\u01b0\u1ee3ng chip c\u00f3 th\u1ec3 s\u1ea3n xu\u1ea5t \u0111\u01b0\u1ee3c t\u1eeb m\u1ed9t t\u1ea5m wafer.<\/p>\n\n\n\n

2. Hi\u1ec3u v\u1ec1 hi\u1ec7u su\u1ea5t s\u1ea3n xu\u1ea5t wafer<\/h2>\n\n\n\n

A T\u1ea5m silicon 300mm<\/strong> l\u00e0 ti\u00eau chu\u1ea9n trong quy tr\u00ecnh s\u1ea3n xu\u1ea5t b\u00e1n d\u1eabn hi\u1ec7n \u0111\u1ea1i, mang l\u1ea1i n\u0103ng su\u1ea5t cao v\u00e0 chi ph\u00ed tr\u00ean m\u1ed7i chip th\u1ea5p h\u01a1n. Tuy nhi\u00ean, t\u1ed5ng s\u1ed1 chip tr\u00ean m\u1ed7i t\u1ea5m wafer ph\u1ee5 thu\u1ed9c v\u00e0o m\u1ed9t s\u1ed1 y\u1ebfu t\u1ed1:<\/p>\n\n\n\n

    \n
  1. K\u00edch th\u01b0\u1edbc khu\u00f4n<\/strong> \u2013 C\u00e1c khu\u00f4n \u0111\u00fac l\u1edbn h\u01a1n chi\u1ebfm nhi\u1ec1u di\u1ec7n t\u00edch t\u1ea5m wafer h\u01a1n, d\u1eabn \u0111\u1ebfn gi\u1ea3m t\u1ed5ng s\u1ed1 chip.<\/li>\n\n\n\n
  2. M\u1ea5t m\u00e1t \u1edf m\u00e9p t\u1ea5m wafer<\/strong> \u2013 C\u00e1c khu\u00f4n g\u1ea7n m\u00e9p tr\u00f2n c\u1ee7a t\u1ea5m wafer th\u01b0\u1eddng kh\u00f4ng th\u1ec3 s\u1eed d\u1ee5ng \u0111\u01b0\u1ee3c.<\/li>\n\n\n\n
  3. M\u1eadt \u0111\u1ed9 khuy\u1ebft t\u1eadt<\/strong> \u2013 Kh\u00f4ng ph\u1ea3i t\u1ea5t c\u1ea3 c\u00e1c khu\u00f4n \u0111\u1ec1u ho\u1ea1t \u0111\u1ed9ng \u0111\u01b0\u1ee3c do c\u00e1c l\u1ed7i trong qu\u00e1 tr\u00ecnh s\u1ea3n xu\u1ea5t.<\/li>\n\n\n\n
  4. \u0110\u1ed9 ph\u1ee9c t\u1ea1p c\u1ee7a quy tr\u00ecnh<\/strong> \u2013 C\u00e1c thi\u1ebft k\u1ebf ph\u1ee9c t\u1ea1p h\u01a1n c\u00f3 th\u1ec3 l\u00e0m gi\u1ea3m nh\u1eb9 n\u0103ng su\u1ea5t.<\/li>\n<\/ol>\n\n\n\n

    3. \u01af\u1edbc t\u00ednh s\u1ed1 l\u01b0\u1ee3ng chip tr\u00ean m\u1ed7i t\u1ea5m wafer<\/h2>\n\n\n\n

    \u0110\u1ec3 \u01b0\u1edbc t\u00ednh s\u1ed1 l\u01b0\u1ee3ng chip tr\u00ean m\u1ed7i t\u1ea5m wafer, h\u00e3y l\u00e0m theo c\u00e1c b\u01b0\u1edbc sau:<\/p>\n\n\n\n

      \n
    1. T\u00ednh di\u1ec7n t\u00edch t\u1ea5m wafer<\/strong>: Di\u1ec7n t\u00edch c\u1ee7a m\u1ed9t t\u1ea5m wafer 300 mm l\u00e0 kho\u1ea3ng 70.685 mm\u00b2 (theo c\u00f4ng th\u1ee9c t\u00ednh di\u1ec7n t\u00edch h\u00ecnh tr\u00f2n: \u03c0 \u00d7 b\u00e1n k\u00ednh\u00b2, trong \u0111\u00f3 b\u00e1n k\u00ednh l\u00e0 150 mm).<\/li>\n\n\n\n
    2. T\u00ednh \u0111\u1ebfn t\u1ed5n th\u1ea5t \u1edf r\u00eca<\/strong>: Th\u00f4ng th\u01b0\u1eddng, kho\u1ea3ng 10% di\u1ec7n t\u00edch t\u1ea5m wafer \u1edf g\u1ea7n c\u00e1c m\u00e9p l\u00e0 kh\u00f4ng th\u1ec3 s\u1eed d\u1ee5ng \u0111\u01b0\u1ee3c. Do \u0111\u00f3, di\u1ec7n t\u00edch c\u00f3 th\u1ec3 s\u1eed d\u1ee5ng l\u00e0 kho\u1ea3ng 63.617 mm\u00b2.<\/li>\n\n\n\n
    3. Chia theo k\u00edch th\u01b0\u1edbc khu\u00f4n<\/strong>: \u0110\u1ed1i v\u1edbi m\u1ed9t CPU m\u00e1y t\u00ednh \u0111\u1ec3 b\u00e0n Skylake ti\u00eau chu\u1ea9n c\u00f3 k\u00edch th\u01b0\u1edbc chip l\u00e0 145 mm\u00b2, h\u00e3y chia di\u1ec7n t\u00edch t\u1ea5m wafer c\u00f3 th\u1ec3 s\u1eed d\u1ee5ng cho k\u00edch th\u01b0\u1edbc chip: 63.617 \u00f7 145 \u2248 438 chip.<\/li>\n\n\n\n
    4. Hi\u1ec7u su\u1ea5t s\u1ea3n xu\u1ea5t<\/strong>: V\u1edbi n\u0103ng su\u1ea5t trung b\u00ecnh t\u1eeb 85\u201390%, s\u1ed1 l\u01b0\u1ee3ng chip ho\u1ea1t \u0111\u1ed9ng tr\u00ean m\u1ed7i t\u1ea5m wafer l\u00e0 kho\u1ea3ng 372\u2013394<\/strong>.<\/li>\n<\/ol>\n\n\n\n
      \n

      L\u01b0u \u00fd: C\u00e1c chip Skylake di \u0111\u1ed9ng c\u00f3 k\u00edch th\u01b0\u1edbc nh\u1ecf h\u01a1n c\u00f3 th\u1ec3 cho ra h\u01a1n 500 chip ho\u1ea1t \u0111\u1ed9ng tr\u00ean m\u1ed7i t\u1ea5m wafer, trong khi c\u00e1c chip m\u00e1y t\u00ednh \u0111\u1ec3 b\u00e0n ho\u1eb7c m\u00e1y ch\u1ee7 cao c\u1ea5p c\u00f3 k\u00edch th\u01b0\u1edbc l\u1edbn h\u01a1n c\u00f3 th\u1ec3 cho ra \u00edt h\u01a1n 350 chip ho\u1ea1t \u0111\u1ed9ng.<\/p>\n<\/blockquote>\n\n\n\n

      4. T\u1ea1i sao ph\u00e9p t\u00ednh n\u00e0y l\u1ea1i quan tr\u1ecdng<\/h2>\n\n\n\n
        \n
      • Ph\u00e2n t\u00edch chi ph\u00ed<\/strong>: Hi\u1ec7u su\u1ea5t s\u1ea3n xu\u1ea5t wafer \u1ea3nh h\u01b0\u1edfng tr\u1ef1c ti\u1ebfp \u0111\u1ebfn chi ph\u00ed s\u1ea3n xu\u1ea5t tr\u00ean m\u1ed7i chip. Hi\u1ec7u su\u1ea5t cao h\u01a1n gi\u00fap gi\u1ea3m chi ph\u00ed v\u00e0 t\u0103ng l\u1ee3i nhu\u1eadn.<\/li>\n\n\n\n
      • L\u1eadp k\u1ebf ho\u1ea1ch chu\u1ed7i cung \u1ee9ng<\/strong>: Vi\u1ec7c n\u1eafm r\u00f5 s\u1ea3n l\u01b0\u1ee3ng ti\u1ec1m n\u0103ng gi\u00fap c\u00e1c nh\u00e0 s\u1ea3n xu\u1ea5t l\u1eadp k\u1ebf ho\u1ea1ch v\u1ec1 kh\u1ed1i l\u01b0\u1ee3ng s\u1ea3n xu\u1ea5t v\u00e0 t\u1ed3n kho.<\/li>\n\n\n\n
      • M\u1edf r\u1ed9ng quy m\u00f4 c\u00f4ng ngh\u1ec7<\/strong>: Khi k\u00edch th\u01b0\u1edbc n\u00fat b\u00e1n d\u1eabn ng\u00e0y c\u00e0ng thu nh\u1ecf (v\u00ed d\u1ee5: 10nm v\u00e0 7nm), k\u00edch th\u01b0\u1edbc chip c\u0169ng gi\u1ea3m theo, gi\u00fap t\u0103ng s\u1ed1 l\u01b0\u1ee3ng chip tr\u00ean m\u1ed7i t\u1ea5m wafer, nh\u01b0ng \u0111\u1ed9 ph\u1ee9c t\u1ea1p c\u1ee7a quy tr\u00ecnh s\u1ea3n xu\u1ea5t c\u00f3 th\u1ec3 \u1ea3nh h\u01b0\u1edfng \u0111\u1ebfn n\u0103ng su\u1ea5t.<\/li>\n<\/ul>\n\n\n\n

        5. Nh\u1eefng y\u1ebfu t\u1ed1 th\u1ef1c ti\u1ec5n<\/h2>\n\n\n\n
          \n
        • S\u1ef1 kh\u00e1c bi\u1ec7t gi\u1eefa c\u00e1c m\u00f4 h\u00ecnh<\/strong>: C\u00e1c chip Skylake d\u00e0nh cho thi\u1ebft b\u1ecb di \u0111\u1ed9ng c\u00f3 k\u00edch th\u01b0\u1edbc nh\u1ecf h\u01a1n, cho ph\u00e9p s\u1ea3n xu\u1ea5t \u0111\u01b0\u1ee3c nhi\u1ec1u chip h\u01a1n tr\u00ean m\u1ed7i t\u1ea5m wafer so v\u1edbi c\u00e1c phi\u00ean b\u1ea3n d\u00e0nh cho m\u00e1y t\u00ednh \u0111\u1ec3 b\u00e0n ho\u1eb7c m\u00e1y ch\u1ee7.<\/li>\n\n\n\n
        • Khu\u00f4n b\u1ecb l\u1ed7i<\/strong>: M\u1ed9t s\u1ed1 khu\u00f4n kh\u00f4ng \u0111\u1ea1t ti\u00eau chu\u1ea9n ch\u1ea5t l\u01b0\u1ee3ng v\u00e0 kh\u00f4ng th\u1ec3 s\u1eed d\u1ee5ng \u0111\u01b0\u1ee3c ho\u1eb7c \u0111\u01b0\u1ee3c b\u00e1n d\u01b0\u1edbi d\u1ea1ng s\u1ea3n ph\u1ea9m c\u1ea5p th\u1ea5p h\u01a1n.<\/li>\n\n\n\n
        • Xu h\u01b0\u1edbng trong t\u01b0\u01a1ng lai<\/strong>: Ng\u00e0nh c\u00f4ng nghi\u1ec7p \u0111ang chuy\u1ec3n h\u01b0\u1edbng sang c\u00e1c t\u1ea5m wafer c\u00f3 k\u00edch th\u01b0\u1edbc l\u1edbn h\u01a1n (450 mm)<\/strong> v\u00e0 c\u00f4ng ngh\u1ec7 \u0111\u00f3ng g\u00f3i ti\u00ean ti\u1ebfn, c\u00f3 th\u1ec3 gi\u00fap t\u0103ng \u0111\u00e1ng k\u1ec3 s\u1ea3n l\u01b0\u1ee3ng tr\u00ean m\u1ed7i t\u1ea5m wafer.<\/li>\n<\/ul>\n\n\n\n

          6. K\u1ebft lu\u1eadn<\/h2>\n\n\n\n

          Vi\u1ec7c \u01b0\u1edbc t\u00ednh s\u1ed1 l\u01b0\u1ee3ng chip Skylake tr\u00ean m\u1ed9t t\u1ea5m wafer 300mm li\u00ean quan \u0111\u1ebfn c\u00e1c y\u1ebfu t\u1ed1 v\u1ec1 h\u00ecnh h\u1ecdc, th\u1ed1ng k\u00ea n\u0103ng su\u1ea5t v\u00e0 ph\u00e2n t\u00edch l\u1ed7i trong th\u1ef1c t\u1ebf. \u0110\u1ed1i v\u1edbi c\u00e1c die Skylake d\u00e0nh cho m\u00e1y t\u00ednh \u0111\u1ec3 b\u00e0n ti\u00eau chu\u1ea9n (~145 mm\u00b2), m\u1ed9t t\u1ea5m wafer 300mm c\u00f3 th\u1ec3 s\u1ea3n xu\u1ea5t \u0111\u01b0\u1ee3c kho\u1ea3ng 372\u2013394 chip ho\u1ea1t \u0111\u1ed9ng. Vi\u1ec7c n\u1eafm r\u00f5 ch\u1ec9 s\u1ed1 n\u00e0y l\u00e0 r\u1ea5t quan tr\u1ecdng \u0111\u1ed1i v\u1edbi vi\u1ec7c l\u1eadp m\u00f4 h\u00ecnh chi ph\u00ed, l\u1eadp k\u1ebf ho\u1ea1ch s\u1ea3n xu\u1ea5t v\u00e0 d\u1ef1 b\u00e1o trong ng\u00e0nh c\u00f4ng nghi\u1ec7p b\u00e1n d\u1eabn.<\/p>\n\n\n\n

          V\u1edbi nh\u1eefng ti\u1ebfn b\u1ed9 trong c\u00f4ng ngh\u1ec7 wafer v\u00e0 c\u00f4ng ngh\u1ec7 quang kh\u1eafc, c\u00e1c th\u1ebf h\u1ec7 CPU trong t\u01b0\u01a1ng lai s\u1ebd \u0111\u1ea1t \u0111\u01b0\u1ee3c n\u0103ng su\u1ea5t cao h\u01a1n v\u00e0 quy tr\u00ecnh s\u1ea3n xu\u1ea5t hi\u1ec7u qu\u1ea3 h\u01a1n, t\u1eeb \u0111\u00f3 ti\u1ebfp t\u1ee5c duy tr\u00ec nh\u1ecbp \u0111\u1ed9 ph\u00e1t tri\u1ec3n nhanh ch\u00f3ng c\u1ee7a ng\u00e0nh c\u00f4ng ngh\u1ec7 m\u00e1y t\u00ednh.<\/p>","protected":false},"excerpt":{"rendered":"

          The production of modern microprocessors, such as Intel\u2019s Skylake series, starts with large silicon wafers. Understanding how many chips a single wafer can yield is crucial for semiconductor manufacturers, hardware designers, and industry analysts. In this article, we will examine the factors that determine the number of Skylake chips produced from a standard 300mm (12-inch) […]<\/p>\n","protected":false},"author":2,"featured_media":8799,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_uag_custom_page_level_css":"","footnotes":""},"categories":[27,12],"tags":[2167,2166,2169,2168,1225,1137,2165],"class_list":["post-8798","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-companynews","category-news","tag-300mm-wafer","tag-cpu-yield","tag-die-per-wafer","tag-intel-skylake","tag-semiconductor-manufacturing","tag-silicon-wafer","tag-skylake"],"acf":[],"uagb_featured_image_src":{"full":["https:\/\/www.sic-wafers.com\/wp-content\/uploads\/2026\/04\/64fbdfb5-c266-4e64-9da9-607bead0a5f6.webp",1447,1086,false],"thumbnail":["https:\/\/www.sic-wafers.com\/wp-content\/uploads\/2026\/04\/64fbdfb5-c266-4e64-9da9-607bead0a5f6-150x150.webp",150,150,true],"medium":["https:\/\/www.sic-wafers.com\/wp-content\/uploads\/2026\/04\/64fbdfb5-c266-4e64-9da9-607bead0a5f6-300x225.webp",300,225,true],"medium_large":["https:\/\/www.sic-wafers.com\/wp-content\/uploads\/2026\/04\/64fbdfb5-c266-4e64-9da9-607bead0a5f6-768x576.webp",768,576,true],"large":["https:\/\/www.sic-wafers.com\/wp-content\/uploads\/2026\/04\/64fbdfb5-c266-4e64-9da9-607bead0a5f6-1024x769.webp",800,601,true],"1536x1536":["https:\/\/www.sic-wafers.com\/wp-content\/uploads\/2026\/04\/64fbdfb5-c266-4e64-9da9-607bead0a5f6.webp",1447,1086,false],"2048x2048":["https:\/\/www.sic-wafers.com\/wp-content\/uploads\/2026\/04\/64fbdfb5-c266-4e64-9da9-607bead0a5f6.webp",1447,1086,false],"trp-custom-language-flag":["https:\/\/www.sic-wafers.com\/wp-content\/uploads\/2026\/04\/64fbdfb5-c266-4e64-9da9-607bead0a5f6-16x12.webp",16,12,true],"woocommerce_thumbnail":["https:\/\/www.sic-wafers.com\/wp-content\/uploads\/2026\/04\/64fbdfb5-c266-4e64-9da9-607bead0a5f6-300x300.webp",300,300,true],"woocommerce_single":["https:\/\/www.sic-wafers.com\/wp-content\/uploads\/2026\/04\/64fbdfb5-c266-4e64-9da9-607bead0a5f6-600x450.webp",600,450,true],"woocommerce_gallery_thumbnail":["https:\/\/www.sic-wafers.com\/wp-content\/uploads\/2026\/04\/64fbdfb5-c266-4e64-9da9-607bead0a5f6-100x100.webp",100,100,true]},"uagb_author_info":{"display_name":"lydia","author_link":"https:\/\/www.sic-wafers.com\/vi\/author\/lydia\/"},"uagb_comment_info":0,"uagb_excerpt":"The production of modern microprocessors, such as Intel\u2019s Skylake series, starts with large silicon wafers. Understanding how many chips a single wafer can yield is crucial for semiconductor manufacturers, hardware designers, and industry analysts. In this article, we will examine the factors that determine the number of Skylake chips produced from a standard 300mm (12-inch)…","_links":{"self":[{"href":"https:\/\/www.sic-wafers.com\/vi\/wp-json\/wp\/v2\/posts\/8798","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.sic-wafers.com\/vi\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.sic-wafers.com\/vi\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.sic-wafers.com\/vi\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/www.sic-wafers.com\/vi\/wp-json\/wp\/v2\/comments?post=8798"}],"version-history":[{"count":1,"href":"https:\/\/www.sic-wafers.com\/vi\/wp-json\/wp\/v2\/posts\/8798\/revisions"}],"predecessor-version":[{"id":8800,"href":"https:\/\/www.sic-wafers.com\/vi\/wp-json\/wp\/v2\/posts\/8798\/revisions\/8800"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.sic-wafers.com\/vi\/wp-json\/wp\/v2\/media\/8799"}],"wp:attachment":[{"href":"https:\/\/www.sic-wafers.com\/vi\/wp-json\/wp\/v2\/media?parent=8798"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.sic-wafers.com\/vi\/wp-json\/wp\/v2\/categories?post=8798"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.sic-wafers.com\/vi\/wp-json\/wp\/v2\/tags?post=8798"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}