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Exceptional 6 inch & 8-inch FZ/CZ Etching Silicon Wafers – High Chemical Purity, Unmatched Performance for MEMS

    Etching silicon wafer‘s abstarct

    XINKEHUI’s etching silicon wafers are meticulously designed to meet high industry standards, available in both N type and P type classifications. These wafers are engineered to have an exceptionally low surface roughness, which enhances their utility in sensitive electronic applications. The wafers are offered with options for both low and high reflectivity, allowing them to be optimally used in various technological environments depending on the specific light absorption and reflection needs.

    The standout feature of these etching wafers is their remarkable glossiness coupled with a relatively low production cost. This combination makes them highly desirable as they provide a cost-effective alternative to more expensive polished or epitaxial wafers. By substituting these higher-cost wafers, XINKEHUI’s etching wafers offer a significant cost advantage in manufacturing processes, particularly in the production of electronic elements where reducing expenses without sacrificing quality is crucial.

    Furthermore, the adoption of these etching wafers can lead to substantial cost savings in the mass production of electronic components, especially in industries looking to optimize material costs while maintaining high performance and reliability in their electronic devices. This makes XINKEHUI’s etching silicon wafers an invaluable resource for companies aiming to enhance their competitive edge in the market.

    Etching Silicon Wafers’ photos

    etching silicon wafer
    etching silicon wafer

    Etching silicon wafer‘s properties

    1. Material Composition: Typically made from high-purity Etching Silicon Wafers, which is essential for achieving the desired electrical properties in semiconductor devices.
    2. Surface Smoothness: Etching wafers often have extremely smooth surfaces, which is crucial for the deposition of thin films and other materials in device fabrication.
    3. Dimensional Stability: They maintain their shape and dimensions under the thermal and chemical stresses encountered during various manufacturing processes.
    4. Thermal Conductivity: Etching Silicon Wafers has good thermal conductivity, which helps dissipate heat generated during device operation, thereby enhancing performance and longevity.
    5. Electrical Properties: The intrinsic semiconductor nature of Etching Silicon Wafers can be modified through doping to create either p-type or n-type materials, which are fundamental for forming p-n junctions in electronic devices.
    6. Chemical Resistance: Etching Silicon Wafers is resistant to oxidation and other chemical reactions at room temperature, although it can be etched with specific chemicals under controlled conditions, which is how patterns are created on the wafer.
    7. Mechanical Strength: Despite being relatively brittle, Etching Silicon Wafers are strong enough to withstand handling and processing without degrading their usability.

    Silicon (Si) is the predominant semiconductor material used in the technology industry, notable for its ability to be processed into single crystal wafers up to 450 mm in diameter. These wafers are remarkably thin, typically less than 1 mm in thickness, and are circular slices derived from a larger single crystal semiconductor ingot. The geometric arrangement of silicon atoms within the crystal is organized into lattice planes and directions, which are mathematically represented using the Miller Index. This indexing system provides a way to describe vectors normal to the surfaces of specific crystal planes or facets within the cubic lattice structure of the Etching Silicon Wafers.

    In this cubic system, a notation such as [hkl] is employed to denote the orientation of a plane or facet, simplifying the characterization and manipulation of the crystal for various applications. Each silicon crystal is composed of fundamental units that repeat periodically, each with a distinct shape, volume, and composition. These fundamental units are crucial for understanding and exploiting the electronic properties of Etching Silicon Wafersin semiconductor manufacturing. This structured approach to describing and cutting the wafers ensures precision in the creation of semiconductor devices, where consistency and accuracy are paramount.

    Crystal Properties

    Space GroupFd3m
    Atomic weight28.0855
    Lattice spacing (a0) at 300K0.54311nm
    Density at 300K2.3290g/cm3
    Nearest Neighbour Distance at 300K0.235nm
    Number of atoms in 1 cm34.995×1022
    Isotopes28 (92.23%)
    29 (4.67%)
    30 (3.10%)
    Electron Shells1s22s22p63s23p2
    Common IonsSi 4 +, Si 4 –
    Critical Pressure1450atm
    Critical Temperature4920°C

    Band Structure Properties

    Dielectric Constant at 300 K (Relative Permittivity (εr))11.7
    Dielectric Strength100 – 700(V/mil)
    Loss Tangent0.005 (at 1 GHz)
    0.015 (at 10 GHz)
    Effective density of states (conduction, Nc T=300 K )2.8×1019cm-3
    Effective density of states (valence, Nv T=300 K )1.04×1019cm-3
    Electron affinity133.6kJ / mol
    Energy Gap Eg at 300 K (Minimum Indirect Energy Gap at 300 K)1.12eV
    Energy Gap Eg at ca. 0 K (Minimum Indirect Energy Gap at 0K)1.17 (at 0 K)eV
    Minimum Direct Energy Gap at 300 K3.4eV
    Energy separation (EΓL)4.2eV
    Intrinsic Debye length24µm
    Intrinsic carrier concentration at 300K1×1010cm-3
    Intrinsic carrier concentration at 25°C8.6×109cm-3
    Intrinsic resistivity3.2×105Ω×cm
    Auger recombination coefficient Cn1.1×10-30cm6 / s
    Auger recombination coefficient Cp3×10-31cm6 / s

    Thermal Properties

    Melting point1414
    Boiling point3538K
    Specific heat0.7J / (g × °C)
    Thermal conductivity [300K]148W / (m × K)
    Thermal diffusivity0.8cm2/s
    Thermal expansion, linear2.6×10-6°C -1
    Debye temperature640K
    Temperature dependence of band gap-2.3e-4eV/K
    Heat of: fusion / vaporization / atomization39.6 / 383.3 / 452kJ / mol

    Electrical Properties

    Breakdown field≈ 3×105V/cm
    Index of refraction3.42
    Mobility electrons≈ 1400cm2 / (V × s)
    Mobility holes≈ 450cm2 / (V × s)
    Diffusion coefficient electrons≈ 36cm2/s
    Diffusion coefficient holes≈ 12cm2/s
    Electron thermal velocity2.3×105m/s
    Hole thermal velocity1.65×105m/s
    Optical phonon energy0.063eV
    Density of surface atoms(100) 6.78
    (110) 9.59
    (111) 7.83
    Work function (intrinsic)4.15eV
    Ionization Energies for Various DopantsDonors:Sb 0.039
    P 0.045
    As 0.054
    Acceptors:B 0.045
    Al 0.067
    Ga 0.072
    In 0.16



    Mechanical Properties

    Bulk modulus of elasticity9.8×1011dyn/cm2
    Hardness7on the Mohs scale
    Surface microhardness (using Knoop’s pyramid test)1150kg/mm2
    Elastic constantsC11 = 16.60×1011
    C12 = 6.40×1011
    C44 = 7.96×1011
    Young’s Modulus (E)[100]
    Shear Modulus64.1GPa
    Poisson’s Ratio0.22 to 0.28

    Our Etching Silicon Wafers manufacturing process

    From sand to ingot

    Silicon, constituting about 27% of the Earth’s crust, ranks as the second most abundant element, following oxygen. It does not occur in its elemental form naturally but exists predominantly as silicon dioxide (SiO2). This compound forms a significant part of sand and various types of rocks.

    For its application in the semiconductor industry, silicon must be extracted and refined to achieve an ultra-high purity level of approximately 99.9999999% (9N). This purification process involves three energy-intensive steps:

    • step1 Sand to Metallurgical grade Silicon

    Silica sand, which naturally contains at least 98% SiO2, is mined in locations that are strategically chosen for their ease of transportation by ship, such as Mexico. The sand is then transported to regions where hydroelectric power is abundant and cost-effective, like the west coast of Norway. Here, the sand is introduced into electric arc furnaces equipped with large carbon electrodes. At high temperatures, a chemical reaction occurs where SiO2 and carbon combine to produce silicon and carbon monoxide, as described by the equation SiO2 + 2C → Si + 2CO. The silicon produced through this process is of metallurgical grade, which is about 99% pure, and is primarily used in the hardening processes of aluminum and steel.

    • step 2 Metalurgical to Semiconductor grade Silicon (Siemens process)

    Metallurgical grade silicon is subjected to a reaction with hydrogen chloride, typically resulting in the formation of trichlorosilane (TCS), as shown by the chemical equation Si + 3HCl → SiHCl3 + H2. TCS, which is a liquid, undergoes several stages of distillation, increasing in purity from the initial 2N (99%) to an impressive 9N (99.9999999%) purity.

    This ultra-pure TCS vapor is then directed over heated silicon rods at a temperature of 1,150ºC. At this high temperature, the TCS dissociates, and silicon begins to deposit on the rods as small crystals. The volatile by-products of this reaction are captured, redistilled, and recycled to enhance efficiency and reduce waste.

    As the silicon rods accumulate more silicon, they grow in size to diameters of either 100mm or 200mm. Once they reach the desired size, they are either used directly for the Float-Zone (FZ) crystallization method or crushed into smaller pieces for use in the Czochralski (CZ) crystallization process. This method of producing high-purity silicon is known as the Siemens process, which is the most common technique for manufacturing semiconductor-grade silicon.

    • step3 Monocrystalline Silicon ingots

    Polycrystalline silicon is transformed into monocrystalline ingots primarily using the Czochralski (CZ) process. In this method, chunks of polysilicon along with a selected dopant are placed into a quartz crucible and melted in an electric furnace under an argon atmosphere. A seed crystal is then carefully inserted into the molten silicon, slowly rotated, and gradually lifted. As it is withdrawn, silicon crystallizes around it, forming a cylindrical single-crystal ingot. The diameter of these ingots can be up to 300mm or even 450mm, depending on the process settings.

    The crystallographic orientation of the ingot matches that of the seed crystal, which can be oriented in the (100), (111), (110), or (211) planes. A precise and controlled amount of a dopant—such as Boron, Phosphorus, Antimony, or Arsenic—is added to the silicon to tailor its electrical conductivity to specific requirements.

    The Floating Zone (FZ) technique is another method used for growing high-purity monocrystalline silicon ingots, especially when high resistivity or minimal oxygen contamination is needed. This crucible-free method involves maintaining a molten zone of silicon between two solid rods, using only surface tension. Dopants are introduced into this zone through a gas, enhancing the ingot’s properties without the risk of oxygen contamination from a quartz crucible, a common issue with the CZ process.

    From ingot to wafer

    Silicon ingots are produced in a variety of sizes, with common nominal diameters including 1″, 2″, 3″, 100mm, 125mm, 150mm, 200mm, 300mm, and 450mm. These ingots are typically crystallized using either the Czochralski (CZ) or Floating Zone (FZ) methods. The crystallographic orientations of the ingots are primarily (100) or (111), though (110) and (211) orientations are also used.

    To achieve p-type conductivity, silicon ingots are doped with Boron (B), resulting in resistivity levels ranging from 0.001 to 10,000 Ohm-cm, with the most common range being 1-10 Ohm-cm. For n-type conductivity, Phosphorus is used as a dopant, allowing for a similar resistivity range, though special safety measures are necessary for manufacturing with resistivities below 0.1 Ohm-cm. Antimony (Sb) and Arsenic (As) are also used to dope silicon to n-type, with resistivities typically around 0.008-0.020 Ohm-cm and 0.001-0.005 Ohm-cm, respectively. Undoped (intrinsic) silicon ingots can exhibit resistivities greater than 20,000 Ohm-cm, in which case the type remains undetermined.

    Boron-doped CZ crystallized silicon ingots, particularly in the 0.1-100 Ohm-cm range, must undergo a heat treatment (quenching) post-crystallization to remove Boron-Oxygen complexes that form during slow cooling. This treatment is routinely performed on ingots up to 4″ in diameter. Larger ingots, however, require the wafers to be heat-treated after slicing, as the ingots themselves cannot be cooled rapidly enough.

    The electronic properties of silicon wafers are primarily determined during the ingot manufacturing process, whereas the wafer manufacturing only affects their geometric properties and crystallographic parameters. Silicon ingots are transformed into silicon wafers through several precise manufacturing steps, ensuring their readiness for use in semiconductor applications.

    Ingot slicingWafer edge roundingWafers lapping & etchingWafers polishing
    Ingots, after the growth, are top and tail cropped, grounded to the diameter and sliced into wafers. There are two slicing methods in use, wire slicing, commonly used in a mass production and ID slicing, apllied for short series. During slicing the ingots are often tilted from their axis to create off-oriented wafers. Off orientation is crucial for some applications (e.g. to zero difraction plates for X-reay), also improves smooth epitaxial growth of silicon on silicon layers.To prevent chipping, the sharp edge of the wafer is grinded to the round shape. There are many edge shapes are possible and applied for different applications. Long, sharp edges improves smooth epitaxial silicon growth, and are often apllied for substrates used for thick epi layer (>20µm). Trapesoidal edge shape is used for very thick wafers (>3000 µm). Such wafers ‘sliced and edge-rounded wafers” are called ‘as-cut’ wafer.
    The wafers are first categorized based on their thickness and then placed into batch lapping machines where they are subjected to a lapping process using quartz-based and fine lapping powders. This process ensures that the wafers are uniform in thickness, surface appearance, and shape. However, to eliminate any subsurface mechanical damage incurred during lapping, the wafers undergo an additional etching step.
    There are two prevalent types of etching methods used: alkaline etching, which involves the use of a potassium hydroxide (KOH) solution, and acid etching, which utilizes a mixture of nitric acid (HNO3), acetic acid (CH3COOH), and hydrofluoric acid (HF). Following these etching processes, the wafers are referred to as “as-etched” wafers.
    These “as-etched” wafers are sufficiently prepared and can be directly used as starting materials for the fabrication of various devices, such as thyristors.
    The majority of applications necessitate silicon wafers to have a smooth, mirror-like finish, with a surface roughness (Ra) of less than 5 Angstroms. To achieve this high level of smoothness, silicon wafers undergo a chemical-mechanical polishing (CMP) process. Typically, in a standard polishing procedure, wafers are polished one side at a time while being attached to polishing blocks.
    An advanced method known as coplanar polishing utilizes a double-sided polisher. This technique simultaneously polishes both sides of the silicon wafers, enhancing efficiency and uniformity. After polishing, the wafers are subjected to a wet cleaning process followed by spin drying to remove any residual particles and contaminants. Once cleaned and dried, the wafers are in optimal condition for the deposition of epitaxial layers, preparing them for further semiconductor fabrication.

    Epitaxial processes

    Epi Wafer

    The term epitaxy comes from the ancient Greek roots epi (ἐπί), meaning „above”and taxis (τάξις), meaning „an ordered manner”. It can be translated as “arranging upon”. For most technological applications, it is desired that the deposited material form a crystalline overlayer that has one well-defined orientation with respect to the substrate crystal structure (single-domain epitaxy). Chemical vapor deposition (CVD) is a key technology used to produce high quality, high-performance, solid materials.

    The process is used in the semiconductor industry to produce thin films. In typical CVD, the wafer (substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit. Frequently, volatile by-products are also produced, which are removed by gas flow through the reaction chamber.

    Back side protectionReactor typesSilicon sources
    Epitaxial Si layer, during the growth, is doped in a controled way, from gas present in ambient atmosphere. The most common are phosphin (PH3) or diboran (B2H4). However, the dopant atoms also migrate from the substrate to the layer, additionally doping the layer, in unwonted way. To prevent this “auto-doping” phenomaena the wafers shall be protected on the backsides. The protection is made by adding additional layer on the wafer’s backside. It can be sealing oxide layer or polysilicon layer or sometimes super sealing oxide and poly together.In common use there are 3 types of silicon on silicon epi reactors: batch reactors: barrel (where wafers are standing vertically) or pan-cake (wafers are in a horisontal) single wafer reactors (pan-cake type but for one wafer only).The sources of silicon for epi are ususally:  
    Trichlorosilan: SiHCl3+H2→↓Si+3HCl
    Tetrachloride: SiCl4+2H2→↓Si+4HCl  
    The advantage of using SiHCl3 to SiCl4 is lower process temperature about 1090 °C to about 1115 °C adequately.
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