Most commercial silicon carbide power devices today are built on n-type 4H-SiC substrates.
However, as SiC power electronics move toward ultra-high-voltage applications, particularly devices operating above several kilovolts, p-type 4H-SiC substrates are attracting increasing attention.
One important example is the n-channel SiC insulated gate bipolar transistor, or SiC IGBT.
Unlike conventional unipolar SiC MOSFETs, ultra-high-voltage IGBTs can benefit from conductivity modulation, making them attractive for applications where blocking voltage becomes extremely high and the resistance of a purely unipolar drift region becomes increasingly difficult to manage.
A major materials challenge, however, is the availability of high-quality, low-resistivity p-type 4H-SiC substrates.
This problem remains substantially more difficult than producing conventional n-type SiC wafers.
Recent research illustrates how quickly this area is progressing. In 2025, researchers demonstrated a heavily aluminum-doped 4H-SiC substrate grown by physical vapor transport with a minimum resistivity of approximately 55.35 mΩ·cm. In 2026, researchers further reported the development of 150 mm p-type 4H-SiC substrates using solution growth, specifically targeting the uniformity and crystal-quality problems that arise when scaling p-type SiC to larger diameters.
For device engineers and substrate buyers, this means that p-type SiC should no longer be evaluated only by diameter and conductivity type.
Important specifications include:
- resistivity,
- resistivity uniformity,
- aluminum concentration,
- acceptor activation,
- crystal polytype stability,
- dislocation density,
- wafer cracking risk,
- flatness,
- surface quality,
- and wafer-to-wafer consistency.
This article explains the most important material considerations when selecting p-type 4H-SiC substrates for ultra-high-voltage power devices.
Why P-Type SiC Is Different from Conventional N-Type SiC
Commercial conductive 4H-SiC substrates are normally n-type.
Nitrogen is the most commonly used donor dopant.
N-type SiC technology has benefited from decades of optimization in:
crystal growth,
doping control,
wafer diameter,
resistivity uniformity,
defect reduction,
and substrate processing.
P-type SiC presents a different materials problem.
To obtain p-type conductivity, acceptor impurities must be incorporated into the SiC crystal.
Aluminum is generally the preferred acceptor because it provides one of the shallowest acceptor levels available in 4H-SiC.
However, aluminum behaves very differently from nitrogen during SiC crystal growth.
Controlling its incorporation into a growing SiC boule is difficult, particularly under the high temperatures required for physical vapor transport.
As a result, achieving all three of the following simultaneously remains challenging:
low resistivity,
uniform resistivity,
and high crystal quality.
This is the fundamental reason why p-type SiC substrates are less mature than standard n-type wafers.
Why Ultra-High-Voltage Devices Need P-Type Substrates
At relatively moderate voltage ratings such as:
650 V,
1200 V,
and 1700 V,
SiC MOSFETs are already commercially successful.
Their unipolar conduction mechanism enables fast switching and relatively low conduction losses.
As blocking voltage increases, however, the drift layer must become thicker and more lightly doped.
This increases drift resistance.
For devices targeting extremely high blocking voltages, bipolar device structures become increasingly attractive because conductivity modulation can significantly reduce resistance in a thick drift region.
One important candidate is the n-channel 4H-SiC IGBT.
A simplified structure may include:
n+ emitter
↓
p-body region
↓
n-type drift region
↓
p+ collector / p-type substrate
The p-type substrate therefore becomes part of the device’s current path.
If the substrate resistivity is too high, it can add substantial series resistance and reduce the benefit of using an IGBT architecture.
Research on low-resistivity p-type SiC specifically identifies substrate resistance as one of the important obstacles to realizing high-performance n-channel SiC IGBTs.
Why SiC IGBTs Become Attractive Above 10 kV
For extremely high-voltage power conversion, the required drift region becomes much thicker than in ordinary 1200 V MOSFETs.
A unipolar device must support the voltage mainly through its lightly doped drift layer.
As the required blocking voltage increases:
drift thickness increases,
doping decreases,
and specific on-resistance increases rapidly.
A bipolar device can inject minority carriers into this drift region.
The resulting conductivity modulation lowers the effective resistance during conduction.
For this reason, SiC IGBT research is particularly relevant to ultra-high-voltage applications such as:
medium-voltage grid conversion,
HVDC systems,
traction infrastructure,
industrial high-voltage converters,
solid-state transformers,
renewable-energy transmission,
and pulsed-power systems.
The exact crossover point between MOSFET and IGBT architectures depends on device design, switching frequency and system requirements.
Therefore, a p-type SiC substrate should not automatically be interpreted as the preferred material for every high-voltage device.
Its strongest value appears where bipolar SiC architectures provide a meaningful system-level benefit.
1. Resistivity Is a Critical P-Type SiC Specification
One of the first specifications in a p-type substrate RFQ should be resistivity.
The unit is normally:
Ω·cm
or
mΩ·cm.
Lower substrate resistivity reduces parasitic series resistance.
For n-channel SiC IGBT development, research literature has identified low-resistivity p-type substrates below approximately 0.2 Ω·cm as important, although exact requirements depend on the device architecture and substrate thickness.
The technical challenge is that low resistivity requires sufficient activated acceptor concentration.
This is considerably more difficult in p-type SiC than simply adding more dopant.
2. Aluminum Is the Main P-Type Dopant
Aluminum is widely used to produce p-type 4H-SiC because Al atoms can substitute onto silicon lattice sites and act as acceptors.
In simplified form:
Al doping
↓
acceptor states
↓
hole carriers
↓
p-type conductivity
However, not every incorporated aluminum atom generates a free hole at room temperature.
This is because the Al acceptor level in 4H-SiC is relatively deep compared with conventional silicon dopants.
Research places the Al acceptor level at roughly 190 meV above the valence band. Consequently, aluminum can exhibit substantial incomplete ionization at room temperature.
This has an important consequence:
Al concentration and free-hole concentration are not the same parameter.
A substrate supplier may report a high aluminum concentration while the electrical resistivity remains considerably higher than expected if acceptor activation is incomplete.
For device manufacturing, electrical characterization is therefore essential.
3. Why Heavy Aluminum Doping Is Required
Because aluminum is not completely ionized at room temperature, relatively heavy doping is required to achieve low resistivity.
At moderate Al concentrations, only a fraction of acceptors may contribute free holes.
Research has shown that at approximately 10^17 cm⁻³ Al concentration, ionization can be very limited at room temperature.
As Al concentration becomes very high, ionization behavior improves and much lower resistivity can be achieved.
But increasing Al concentration creates another problem.
Heavy doping can disturb the SiC crystal lattice.
Therefore, the challenge is not simply:
“How much aluminum can be added?”
The real question is:
“How much electrically active aluminum can be incorporated while maintaining 4H crystal stability and acceptable defect density?”
4. Heavy Al Doping Can Create Crystal Stress
Aluminum atoms differ in size from the silicon atoms they replace.
High Al concentrations can therefore alter the local lattice structure.
The consequences may include:
lattice strain,
internal stress,
dislocation formation,
cracking,
polytype instability,
and mechanical-property changes.
Recent experimental research has shown that increasing Al doping can reduce the hardness and fracture toughness of p-type 4H-SiC and can facilitate dislocation formation and crack propagation.
This is particularly important for wafer manufacturing.
A crystal may achieve excellent electrical resistivity while becoming more difficult to:
slice,
grind,
lap,
polish,
thin,
or handle.
For commercial wafers, electrical optimization and mechanical reliability therefore need to be developed together.
5. Polytype Stability Is a Major Challenge
For power electronics, 4H-SiC is normally the desired polytype.
Heavy Al incorporation can increase the risk of unwanted polytype formation during crystal growth.
Possible consequences include local transformation or inclusions involving other SiC polytypes.
This is undesirable because a wafer containing mixed polytypes can exhibit non-uniform:
band structure,
electrical properties,
mechanical behavior,
and epitaxial growth behavior.
Recent PVT research has therefore focused not only on lowering resistivity but also on achieving low-resistivity p-type material without foreign polytype inclusions.
When sourcing p-type wafers, buyers should ask whether the material has been inspected for polytype inclusions rather than assuming that the entire wafer is uniform 4H-SiC.
6. Resistivity Uniformity Is as Important as Minimum Resistivity
A wafer with a very low minimum resistivity is not necessarily a production-quality wafer.
Consider a wafer where:
center resistivity = 0.06 Ω·cm
and
edge resistivity = 0.15 Ω·cm.
The supplier might advertise:
“Minimum resistivity: 0.06 Ω·cm.”
But a device manufacturer sees a different problem:
the electrical behavior varies substantially across the wafer.
This can affect:
current conduction,
device voltage drop,
device-to-device uniformity,
wafer-level yield,
and electrical binning.
Recent research on large-diameter p-type SiC explicitly identifies doping and resistivity non-uniformity as one of the key barriers to practical device manufacturing.
Therefore, an RFQ should preferably specify both:
target resistivity
and
within-wafer resistivity uniformity.
7. Why Al Distribution Can Become Non-Uniform
During SiC crystal growth, dopant incorporation depends on several interacting factors.
These can include:
temperature distribution,
growth rate,
Al vapor pressure,
radial thermal gradients,
crystal surface morphology,
mass transport,
source depletion,
and crystal diameter.
As the boule diameter increases, controlling these conditions becomes more difficult.
The center and edge of the growing crystal may therefore incorporate different amounts of Al.
This can generate a radial resistivity profile.
For small experimental crystals, such variation may be manageable.
For 100 mm or 150 mm production wafers, it becomes a major yield issue.
8. Scaling P-Type SiC to 150 mm
Diameter scaling is one of the most important recent developments.
In 2026, researchers reported high-quality 150 mm p-type 4H-SiC substrates produced using solution growth.
The work focused specifically on the challenges associated with maintaining crystal quality and resistivity control when increasing diameter.
This matters because moving from research-size material to 150 mm wafers changes the commercial potential substantially.
A 150 mm wafer format is compatible with many established SiC device-processing lines.
However, diameter alone does not indicate production maturity.
Customers still need to evaluate:
resistivity map,
usable area,
defect density,
wafer flatness,
surface quality,
repeatability,
and lot consistency.
9. PVT vs Solution Growth
Two different crystal-growth approaches are particularly relevant to p-type SiC development.
Physical Vapor Transport
PVT is the established method used for most commercial SiC substrate production.
Advantages include:
mature equipment,
existing manufacturing knowledge,
commercial scalability,
and compatibility with current SiC boule production.
However, heavy Al doping is difficult to control.
Al can be depleted during growth, and high concentrations can destabilize crystal growth.
Recent PVT developments have used modified crucible designs and carefully controlled growth conditions to improve Al incorporation and lower p-type resistivity.
Solution Growth
Solution growth provides another approach to controlling crystal morphology and impurities.
Recent 150 mm research indicates that solution growth may offer a path toward improved p-type crystal quality and larger-diameter substrates.
However, solution-grown material still needs to satisfy practical manufacturing requirements including:
growth rate,
cost,
diameter scalability,
usable boule thickness,
wafer yield,
and process repeatability.
At present, buyers should evaluate the actual wafer specification rather than assuming that one growth method is universally superior.
10. Defect Control in P-Type 4H-SiC
The same major crystallographic defects encountered in conventional 4H-SiC can also occur in p-type material.
Important defects include:
micropipes,
threading screw dislocations,
threading edge dislocations,
basal plane dislocations,
stacking faults,
polytype inclusions,
and other crystal imperfections.
Heavy Al doping adds another layer of complexity because doping-induced stress can affect defect formation and propagation.
For ultra-high-voltage devices, defect control becomes particularly important because the active structures can be large and the drift layers can be very thick.
A defect that intersects an electrically critical region may reduce breakdown voltage or device yield.
11. Basal Plane Dislocations
Basal plane dislocations, or BPDs, are an important consideration for bipolar SiC devices.
Under minority-carrier injection, BPD-related mechanisms can lead to stacking-fault expansion.
This phenomenon has historically been associated with bipolar degradation in SiC devices.
Because SiC IGBTs rely more heavily on bipolar carrier injection than conventional MOSFET conduction, BPD control can become especially important.
For IGBT-oriented substrates, customers should therefore consider asking for:
BPD density,
measurement method,
mapping data,
and wafer-level distribution.
A single average defect-density number may not provide enough information for large-area devices.
12. Threading Screw and Threading Edge Dislocations
Threading screw dislocations and threading edge dislocations extend approximately through the thickness of the crystal.
Their electrical impact depends on the device structure and location.
For ultra-high-voltage devices, the acceptable density may differ from the requirements for standard 1200 V MOSFETs.
The correct defect specification should therefore be developed with the device process rather than copied directly from a generic SiC substrate datasheet.
13. Surface Quality Still Matters
P-type conductivity does not reduce the importance of wafer surface quality.
The epi-ready surface must support subsequent epitaxial growth.
Relevant specifications include:
surface roughness,
scratches,
pits,
particles,
CMP damage,
subsurface damage,
and step morphology.
Typical evaluation techniques may include:
AFM,
optical defect inspection,
X-ray topography,
Raman spectroscopy,
and surface microscopy.
For an epi-ready p-type substrate, the Si-face normally needs to be CMP polished to semiconductor-grade quality.
14. Aluminum Doping Can Affect Wafer Processing
Heavy Al doping can influence more than electrical properties.
The changing mechanical behavior of the crystal can affect:
slicing,
grinding,
lapping,
CMP,
edge processing,
and wafer thinning.
Research published in 2025 found that higher Al doping can reduce fracture toughness and promote crack propagation in p-type 4H-SiC.
This suggests that processing parameters optimized for standard n-type wafers should not automatically be assumed to be optimal for heavily doped p-type substrates.
For example, manufacturers may need to reconsider:
grinding pressure,
abrasive selection,
material-removal rate,
CMP conditions,
edge geometry,
and wafer-handling procedures.
15. Substrate Thickness
Substrate thickness creates both electrical and mechanical considerations.
A thicker p-type substrate provides greater mechanical strength during wafer processing.
However, if the substrate is electrically resistive, additional thickness increases series resistance.
For vertical power devices, the substrate is therefore frequently thinned after frontside device fabrication.
A complete purchasing specification should include:
incoming thickness,
thickness tolerance,
TTV,
bow,
warp,
and backside surface condition.
The downstream thinning requirement should also be considered during substrate qualification.
16. TTV, Bow and Warp
Ultra-high-voltage device development still relies on standard semiconductor manufacturing equipment.
Therefore, wafer geometry remains important.
TTV
Total Thickness Variation describes variation in wafer thickness.
Poor TTV can affect:
lithography,
epitaxy,
implantation,
backside thinning,
and final device thickness.
Bow and Warp
Bow and warp describe wafer shape.
These parameters can be influenced by:
crystal-growth stress,
heavy doping,
slicing damage,
grinding,
CMP,
and film stress.
Because heavy Al doping can alter crystal stress and mechanical properties, wafer flatness should be verified rather than assumed from conventional n-type SiC performance.
17. P-Type Substrate vs P-Type Epitaxial Layer
These two products should not be confused.
P-Type SiC Substrate
A p-type substrate is a bulk single-crystal wafer whose conductivity is p-type.
It may be used as the mechanical and electrical foundation of a vertical device such as an n-channel IGBT.
P-Type SiC Epitaxial Layer
A p-type epitaxial layer is a thin or thick p-type SiC layer grown on another substrate.
It may form:
device junctions,
collector structures,
buffer layers,
or other functional regions.
A device may require both a p-type substrate and additional epitaxial layers with completely different doping concentrations.
Therefore, an RFQ should clearly distinguish:
substrate doping
from
epitaxial doping.
18. P-Type Substrates for N-Channel SiC IGBTs
One of the most discussed applications for low-resistivity p-type 4H-SiC is the n-channel IGBT.
The device architecture takes advantage of the higher electron mobility of n-channel structures while using bipolar conductivity modulation to reduce drift-region resistance.
A simplified stack may contain:
n+ emitter
p-body
n-type drift epilayer
buffer layer
p+ collector/substrate
Achieving a low-resistance p-type substrate is important because the substrate forms part of the vertical conduction path.
If substrate resistance remains too high, the additional voltage drop can offset the electrical advantages of the bipolar architecture.
This is why progress in p-type substrate growth can directly influence the feasibility of ultra-high-voltage SiC IGBTs.
19. Other Potential Applications
Although SiC IGBTs are a major research target, p-type substrates may also support other device concepts.
Possible areas include:
ultra-high-voltage bipolar transistors,
thyristor-type structures,
GTO devices,
specialized junction devices,
research structures,
and novel vertical bipolar power-device architectures.
The exact material requirements can vary significantly.
A p-type substrate optimized for an IGBT is therefore not automatically ideal for every bipolar SiC device.
20. Why P-Type SiC Is Not Yet as Common as N-Type SiC
Several factors explain the difference.
First, commercial demand for standard n-type SiC MOSFETs and diodes is currently much larger.
Second, nitrogen doping is easier to control during conventional SiC boule growth.
Third, heavy aluminum doping introduces significant challenges involving:
dopant uniformity,
acceptor activation,
crystal strain,
polytype stability,
cracking,
and mechanical properties.
Fourth, ultra-high-voltage SiC IGBT manufacturing itself remains less mature than mainstream 650–1700 V SiC MOSFET production.
This creates a development cycle:
device manufacturers need better p-type substrates,
while substrate manufacturers need sufficient device demand to justify scaling production.
Recent advances in low-resistivity and 150 mm p-type material suggest that this gap is gradually narrowing.
Recommended RFQ Parameters for P-Type 4H-SiC Substrates
A useful RFQ should specify more than:
“Need P-type SiC wafer.”
Basic Crystal Information
Material: 4H-SiC
Conductivity: P-type
Dopant: Al or specified acceptor
Diameter: 2 inch / 3 inch / 4 inch / 6 inch depending on availability
Surface orientation
Off-axis angle
Off-axis direction
Si-face or C-face
Electrical Properties
Target resistivity
Resistivity tolerance
Within-wafer resistivity uniformity
Carrier concentration if required
Al concentration if required
Measurement method
Resistivity map requirement
Crystal Quality
Micropipe density
BPD density
TSD density
TED density
Stacking-fault specification
Polytype inclusion requirement
X-ray rocking curve if required
X-ray topography if required
Geometry
Diameter tolerance
Thickness
Thickness tolerance
TTV
Bow
Warp
Edge exclusion
Edge profile
Surface
SSP or DSP
Si-face CMP requirement
Frontside roughness
Backside roughness
Scratch specification
Pit specification
Particle requirement
Subsurface damage requirement
Documentation
Wafer ID
Crystal lot
Growth method
Dopant information
Resistivity map
Defect map
Surface inspection report
Certificate of Analysis
Lot traceability
Example P-Type SiC RFQ
A customer developing an ultra-high-voltage device could send an inquiry such as:
Product: P-type 4H-SiC substrate
Application: ultra-high-voltage n-channel SiC IGBT development
Diameter: 100 mm or 150 mm
Conductivity: P-type
Dopant: Al
Resistivity: customer-specified low-resistivity range
Resistivity uniformity: full-wafer mapping required
Orientation: (0001)
Off-axis: customer-specified
Surface: Si-face CMP, epi-ready
Thickness: customer-specified
TTV: specified
Bow/Warp: specified
Micropipe density: specified
BPD/TSD/TED: report required
Polytype inclusions: none within specified usable area
Inspection: resistivity map + XRT/defect report
Quantity: R&D / qualification / production lot
Such an RFQ gives the substrate supplier enough information to determine whether existing material can meet the project requirements.
What Should Buyers Ask the Supplier?
For p-type SiC, the following questions are particularly useful.
What is the typical resistivity rather than only the minimum value?
A single minimum value can hide poor wafer uniformity.
Can you provide a full-wafer resistivity map?
This is particularly important for larger diameters.
What is the Al concentration and how is it measured?
Electrical resistivity and chemical dopant concentration should not be treated as the same quantity.
Does the crystal contain foreign polytype inclusions?
Heavy Al doping can make polytype control more difficult.
What is the usable wafer area?
Edge regions may show different doping or crystal quality.
What are the BPD, TSD and TED levels?
This is especially important for bipolar device development.
Can you provide multiple wafers from the same boule?
This helps evaluate wafer-to-wafer and axial resistivity consistency.
Is the wafer epi-ready?
Research-grade polished material and semiconductor epi-ready material are not necessarily equivalent.
P-Type SiC vs N-Type SiC Substrate
The two substrate types serve different device architectures.
N-type 4H-SiC is widely used for:
MOSFETs,
Schottky diodes,
JBS diodes,
and many vertical unipolar power devices.
P-type 4H-SiC is of particular interest for:
n-channel IGBTs,
bipolar devices,
ultra-high-voltage structures,
and specialized research devices.
The selection therefore depends on the device architecture rather than one conductivity type being universally better than the other.
From a manufacturing perspective, n-type substrates are currently much more mature.
P-type substrates require substantially more attention to:
resistivity,
dopant distribution,
polytype stability,
crystal stress,
and defect control.
Low Resistivity Is Not Enough
Perhaps the most important point for p-type SiC purchasing is that a record-low resistivity number does not automatically indicate the best substrate.
Consider two materials.
Wafer A
Minimum resistivity: 0.05 Ω·cm
Maximum resistivity: 0.16 Ω·cm
High radial variation
Several local crystal defects
Wafer B
Resistivity: 0.08–0.10 Ω·cm
Good radial uniformity
Low defect density
Stable 4H polytype
For semiconductor manufacturing, Wafer B may be more useful even though Wafer A has the lower advertised minimum resistivity.
Production material must balance:
electrical performance,
uniformity,
crystal quality,
mechanical integrity,
surface quality,
and repeatability.
This is why recent p-type SiC research increasingly focuses on both doping control and defect control rather than chasing resistivity alone.
The 2026 Outlook for P-Type SiC
P-type 4H-SiC remains considerably less mature than conventional n-type SiC.
However, recent developments are important.
Research has demonstrated:
lower-resistivity heavily Al-doped PVT material,
improved understanding of Al-induced mechanical effects,
and 150 mm p-type 4H-SiC growth aimed at ultra-high-voltage devices.
The key development challenge is shifting from proving that p-type SiC can be produced toward proving that it can be produced with:
large diameter,
low resistivity,
uniform doping,
low defect density,
adequate mechanical strength,
and reproducible wafer-to-wafer quality.
That transition will determine whether p-type SiC becomes a practical platform for future ultra-high-voltage bipolar power electronics.
Conclusion
P-type 4H-SiC substrates could play an important role in the next generation of ultra-high-voltage silicon carbide devices.
Their most significant potential application is the n-channel SiC IGBT, where a low-resistance p-type substrate can support a bipolar device architecture designed for voltage classes beyond the range where conventional unipolar MOSFET structures are most attractive.
However, manufacturing p-type SiC is fundamentally more difficult than producing standard nitrogen-doped n-type substrates.
The core challenge is balancing:
heavy aluminum incorporation,
acceptor activation,
low resistivity,
resistivity uniformity,
4H polytype stability,
defect density,
mechanical integrity,
and wafer-scale processability.
For buyers, this means that selecting p-type SiC by diameter and minimum resistivity alone is not sufficient.
A practical substrate qualification should evaluate:
resistivity maps,
Al doping,
BPD/TSD/TED,
polytype inclusions,
wafer cracking,
TTV,
bow and warp,
CMP surface quality,
and lot-to-lot repeatability.
As 150 mm p-type SiC development advances and low-resistivity growth techniques improve, the material may become increasingly important for SiC IGBTs and other ultra-high-voltage power semiconductor architectures.