Silicon carbide (SiC) power devices are rapidly expanding their share of the global power electronics market. By surpassing the physical performance limits of conventional silicon devices, SiC enables higher efficiency, higher voltage operation, and improved thermal performance in applications such as electric vehicles, renewable energy systems, and industrial power conversion.
Despite these advantages, the relatively high cost of SiC devices remains a major barrier to widespread adoption. One of the key contributors to cost is yield loss during device fabrication, which is often associated with crystalline defects originating from both the substrate and the epitaxial layer. As a result, significant research efforts are focused on improving epitaxial growth technologies and reducing defect densities in SiC materials.
Defects in Silicon Carbide Materials
Due to the intrinsic physical properties of silicon carbide, a variety of crystal defects can form during crystal growth and epitaxy. Typical defects include:
- Mikrorör
- Triangulära defekter
- Morotsdefekter
- Fel vid stapling
- Dislocations
Among these, dislocations are particularly critical and can be classified into three major types:
- Dislokationer i basalplanet (BPD)
- Threading screw dislocations (TSDs)
- Threading edge dislocations (TEDs)
Basal plane dislocations are often considered the most detrimental defects for power devices because they can trigger bipolar degradation in SiC devices. When bipolar conduction occurs, these defects can expand into stacking faults, leading to device performance degradation and reliability issues.
Therefore, reducing the density of basal plane dislocations has become a central objective in SiC material engineering.
Progress in SiC-substrat Tillverkning
Over the past two decades, substantial progress has been made in both wafer diameter scaling and defect reduction in SiC substrates.
The bulk growth of SiC crystals typically relies on the physical vapor transport (PVT) sublimation process. A major milestone occurred in 2004 when researchers from Toyota Central R&D Labs reported the development of SiC seeds with extremely low defect densities and no micropipes. This breakthrough enabled more stable crystal growth and significantly improved substrate quality.
As a result of these advances, commercially available 150 mm and emerging 200 mm SiC substrates now exhibit dramatically reduced defect densities. Modern wafers are essentially free of micropipes and typically show:
- Basal plane dislocation density below 500 cm⁻²
- Threading edge and screw dislocation densities below 5000 cm⁻²
These improvements have paved the way for higher-yield device manufacturing.
Silicon Face vs. Carbon Face in SiC Wafers
Because of the polar nature of the Si–C bond, the top surface of SiC wafers can exhibit either silicon-face (Si-face) eller carbon-face (C-face) polarity. These two surfaces display different physical and chemical behaviors that influence epitaxial growth and device fabrication.
One important difference lies in oxidation behavior. The carbon face oxidizes significantly faster than the silicon face due to a higher concentration of dangling bonds, which affects interface passivation and oxide formation.
Surface morphology also differs between the two orientations. Silicon-face surfaces tend to exhibit higher surface roughness and greater crack density, particularly near wafer edges. In contrast, carbon-face surfaces often support smoother epitaxial growth.
However, carbon-face substrates may also exhibit inclusions of different SiC polytypes, such as 4H-SiC inclusions across the wafer, which must be carefully managed during growth.
Advantages of Carbon-Face Epitaxy
Most commercial SiC power devices today are fabricated on Si-face substrates, primarily because they provide better interface quality and a larger band offset with the gate oxide.
However, carbon-face substrates offer several advantages, particularly for trench MOSFET structures. In trench devices, the gate stack is formed on crystallographic planes that expose characteristics similar to the carbon face.
Because the carbon face oxidizes more rapidly, oxide layers can form more efficiently at the trench bottom, often becoming significantly thicker than those on the sidewalls. This property simplifies fabrication and improves gate oxide breakdown voltage.
Recent collaborative work between research institutions and industry partners has demonstrated near-defect-free SiC epitaxy on 150 mm carbon-face substrates using commercial hot-wall CVD systems.
In these processes:
- A thin buffer layer (~0.5 μm) is first grown
- A thick drift layer (~11 μm) is then deposited
- Growth rates can reach 50 μm per hour, which is exceptionally high for SiC epitaxy
The resulting epitaxial layers exhibit extremely smooth surfaces, with root-mean-square roughness values below 0.3 nm.
Electrical measurements show background doping concentrations around 1.5 × 10¹⁵ cm⁻³, enabling precise control of the drift layer doping in the range of 1–2 × 10¹⁶ cm⁻³, which is suitable for MOSFET device structures.
Most importantly, advanced inspection tools reveal defect densities below 0.1 cm⁻², nearly an order of magnitude lower than typical Si-face epitaxial layers.
Role of Surface Preparation and CMP Optimization
One key factor enabling ultra-low defect epitaxy is the reduction of surface and subsurface damage in the SiC substrate.
This is achieved through optimized chemical mechanical polishing (CMP) processes. CMP involves alternating cycles of surface oxidation and oxide removal to gradually smooth the wafer surface.
For carbon-face SiC, CMP processes can be specially tuned to take advantage of its faster oxidation rate. The result is a smoother surface with significantly reduced subsurface crystal damage, which directly improves epitaxial growth quality.
During epitaxy, basal plane dislocations can be transformed into threading edge dislocations through optimized hydrogen etching and high growth rates. Since threading edge dislocations are less harmful for device operation, this conversion significantly improves material quality.
Another advantage of carbon-face growth is the step-flow growth mode, enabled by longer adatom diffusion lengths exceeding one micrometer. This growth mechanism further suppresses defect formation during epitaxy.
Improvements in Silicon-Face Epitaxy
While carbon-face epitaxy shows promising results, improvements are also being made in traditional silicon-face epitaxial processes, particularly for 200 mm wafers.
A key strategy involves converting basal plane dislocations present in the substrate into threading edge dislocations within the buffer layer before the drift layer is grown.
This concept builds on earlier research that demonstrated how selective etching around BPD regions can encourage this conversion. Although early methods relied on chemical treatments that were difficult to scale for industrial production, newer techniques employ in-situ hydrogen etching within the epitaxial reactor.
Modern processes typically include:
- High-temperature hydrogen etching during wafer bake
- Additional etching between buffer-layer growth steps
- Surface recovery via controlled material reflow
Using these methods, researchers have demonstrated epitaxial wafers with nearly 100% elimination of basal plane dislocations in the active device layers.
Defect densities can be reduced from typical levels of 1 cm⁻² to approximately 0.3–0.4 cm⁻², significantly improving device yield.
SmartSiC: Engineered Substrates for Next-Generation Devices
Another promising approach for eliminating basal plane dislocations is the use of engineered SiC substrates, such as SmartSiC technology.
SmartSiC substrates are produced through wafer bonding and layer transfer techniques. In this process, a thin single-crystal SiC layer is transferred from a donor wafer onto a heavily doped polycrystalline SiC substrate.
The resulting structure offers several advantages:
- Highly conductive poly-SiC substrates enable direct backside ohmic contacts
- Reduced on-resistance in SiC MOSFETs
- Simplified device fabrication
In advanced implementations, the transferred layer originates from carbon-face epitaxial SiC, allowing the substrate to retain the advantages of carbon-face growth while benefiting from the mechanical and electrical properties of engineered substrates.
Recent experimental results demonstrate donor wafers with extremely low defect densities and high doping levels exceeding 6 × 10¹⁸ cm⁻³, meeting the requirements for SmartSiC technology.
Outlook
Although achieving completely defect-free SiC wafers remains a long-term goal, significant progress has already been made in both substrate manufacturing and epitaxial growth technologies.
Advances in carbon-face epitaxy, optimized CMP processes, in-situ defect conversion techniques, and engineered substrates such as SmartSiC are collectively pushing the industry toward near-defect-free SiC materials.
As these technologies mature, they will help reduce manufacturing costs, improve device yield, and accelerate the adoption of SiC power devices across a wide range of high-efficiency power electronics applications.