How to Qualify an 8-Inch SiC Wafer Supplier in 2026: Defect Maps, TTV, Bow, Warp, Epi Quality, CoA and Lot Traceability

The transition from 150 mm to 200 mm (8-inch) silicon carbide wafers is changing how semiconductor manufacturers evaluate SiC substrate suppliers.

At 150 mm, a buyer may sometimes begin qualification with basic parameters such as diameter, thickness, resistivity, surface roughness and micropipe density.

For 200 mm production, that is no longer enough.

As wafer diameter increases, substrate geometry, defect distribution, polishing uniformity, epitaxial consistency and lot-to-lot repeatability become increasingly important. A supplier may be able to deliver several good samples without necessarily demonstrating the process stability required for production-scale supply.

This means that qualifying an 8-inch SiC wafer supplier should focus on one central question:

Can the supplier repeatedly deliver wafers that meet the agreed specification across the full wafer, across the full lot and across multiple production lots?

The answer requires more than a specification sheet.

Buyers should examine:

• crystal and electrical specifications,
• defect maps,
• TTV,
• bow and warp,
• surface quality,
• epitaxial performance,
• inspection methods,
• Certificate of Analysis data,
• wafer identification,
• lot traceability,
• packaging,
• change control,
• and long-term consistency.

1. Start With the Exact 200mm SiC Wafer Specification

The first step is to define exactly what type of wafer is required.

“8-inch SiC wafer” is not a complete RFQ.

A meaningful request should specify at least:

Do not begin supplier comparison until all candidates are quoting against the same specification.

Otherwise, a lower-priced wafer may simply have wider tolerances or less inspection.

2. “Epi-Ready” Is Not a Complete Quality Definition

Many suppliers describe SiC substrates as:

epi-ready

This usually implies that the Si-face has received CMP or another final polishing process appropriate for epitaxial growth.

However, “epi-ready” by itself does not tell the buyer:

• surface roughness,
• AFM scan size,
• residual scratch level,
• particle count,
• surface contamination,
• polishing pits,
• subsurface damage,
• edge roll-off,
• defect density,
• or wafer geometry.

Two suppliers can both call a 200 mm wafer “epi-ready” while delivering significantly different surface and flatness performance.

The buyer should therefore convert the word epi-ready into measurable acceptance criteria.

For example:

Surface: Si-face CMP
Ra: ≤ agreed limit
AFM scan: defined scan area
Scratches: agreed maximum
Particles: size threshold + maximum count
Metal contamination: agreed analytical limit
Edge defects: no cracks or chips above agreed dimensions

This creates a specification that can actually be inspected.

3. Ask for a Full-Wafer Defect Map

For 8-inch SiC, an average defect-density number is often insufficient.

Consider two wafers with exactly the same average defect density.

One wafer may have defects distributed relatively uniformly.

The other may contain a large defect cluster in one region.

The average number can be identical, but the implications for device yield can be very different.

This is why buyers should request a wafer defect map whenever practical.

A defect map can help identify:

• defect clusters,
• edge-related defects,
• localized polishing damage,
• crystal-growth sectors,
• high-defect regions,
• recurring spatial patterns,
• abnormal wafers within a lot.

For device manufacturers, the spatial distribution of defects may be as important as the total count.

4. Understand the Important SiC Crystal Defects

SiC crystal quality cannot be reduced to micropipe density alone.

Important defects may include:

Micropipes

Micropipes are hollow-core defects historically associated with serious device-yield problems.

Modern high-quality SiC has greatly reduced micropipe density, but the parameter may still appear in substrate specifications.

Basal Plane Dislocations — BPD

BPDs are particularly important for bipolar degradation and epitaxial quality.

Depending on the intended power device, BPD control can be a critical qualification parameter.

Threading Screw Dislocations — TSD

TSDs propagate approximately along the crystal growth direction and can influence local device characteristics and epitaxial morphology.

Threading Edge Dislocations — TED

TED density is usually much higher than micropipe density and should be evaluated according to the intended device design and voltage class.

Stacking Faults

Stacking faults may originate from substrate defects or develop during epitaxy and device operation.

For serious qualification programs, the supplier should be able to explain:

• which defects are inspected,
• the inspection method,
• sampling frequency,
• detection threshold,
• reporting format.

A simple statement such as “low defect density” is not sufficient.

5. Do Not Evaluate Defect Density Without Knowing the Inspection Method

Defect numbers are useful only when the measurement method is understood.

Possible methods include:

• optical inspection,
• laser scattering,
• photoluminescence,
• X-ray topography,
• KOH etching,
• Nomarski microscopy,
• automated defect inspection.

Different techniques detect different defect classes and may use different thresholds.

Therefore, when comparing Supplier A and Supplier B, ask:

How was this value measured?

For example:

Supplier A:

BPD ≤ X cm⁻²

Supplier B:

BPD ≤ Y cm⁻²

The smaller number does not automatically mean Supplier B is better.

You also need to know:

• measurement method,
• sampled area,
• exclusion zone,
• detection threshold,
• statistical basis,
• whether the value is guaranteed or typical.

6. TTV Is Critical for 200mm SiC

TTV — Total Thickness Variation describes the difference between the maximum and minimum thickness across the wafer.

It is one of the most important parameters when qualifying an 8-inch substrate.

Excessive TTV may affect:

• wafer chucking,
• epitaxy,
• lithography,
• implantation,
• grinding,
• backside processing,
• wafer thinning,
• device uniformity.

A supplier should not merely report nominal thickness such as:

500 µm ± 25 µm

because thickness tolerance and TTV are not the same measurement.

A wafer could remain within the allowed overall thickness tolerance while still having poor thickness uniformity across its diameter.

Therefore, an RFQ should specify both:

Thickness tolerance

and

Maximum TTV

7. Bow and Warp Must Be Evaluated Separately

Bow and warp are frequently placed next to each other on wafer specifications, but they describe different aspects of wafer shape.

Bow

Bow represents the deviation of the wafer’s median surface relative to a reference plane.

It provides an indication of the wafer’s overall curvature.

Warp

Warp describes the total difference between the highest and lowest positions of the wafer’s median surface.

Warp therefore captures more complex wafer deformation.

A wafer can have acceptable bow but unacceptable warp.

This is particularly important at 200 mm because larger wafers are more sensitive to:

• residual crystal stress,
• slicing stress,
• grinding non-uniformity,
• CMP conditions,
• thermal processing,
• epitaxial stress.

Ask the supplier for actual measurement distributions rather than only maximum specification values.

For example:

This tells you much more than:

TTV ≤ X µm
Bow ≤ Y µm
Warp ≤ Z µm

A capable supplier should understand the difference between specification limit and actual measured value.

8. Ask for Distribution Data, Not Only Pass/Fail

One of the most useful questions during supplier qualification is:

How close is the production distribution to the specification limit?

Suppose your requirement is:

Warp ≤ 40 µm.

Supplier A typically produces:

18–25 µm.

Supplier B typically produces:

35–39 µm.

Both suppliers technically pass.

But they do not necessarily offer the same process margin.

This concept applies to:

• TTV,
• bow,
• warp,
• resistivity,
• defect density,
• particle counts,
• roughness,
• epi thickness,
• epi doping.

Process capability is usually more informative than a single passing sample.

9. Resistivity Must Be Evaluated Across the Wafer

For conductive N-type 4H-SiC substrates, buyers commonly specify a resistivity range.

However, a supplier qualification should consider both:

absolute resistivity

and

resistivity uniformity.

A single center-point measurement does not characterize the entire 200 mm substrate.

Ask:

• how many points are measured,
• whether measurements cover center and edge,
• what instrument is used,
• whether a resistivity map is available,
• how wafer-to-wafer variation is controlled.

For power devices, inconsistent substrate resistivity can contribute to electrical variability and complicate device-process control.

10. Surface Roughness Requires Measurement Conditions

Surface roughness is frequently given as:

Ra ≤ 0.2 nm

or another limit.

But the number is incomplete unless the measurement condition is defined.

Important information includes:

• AFM scan size,
• number of measurement locations,
• center versus edge measurement,
• filtering method,
• whether scratches are included or separately classified.

An RFQ might therefore specify:

Si-face Ra measured by AFM over an agreed scan area at agreed wafer locations.

This makes qualification data more comparable.

11. Check Edge Quality and Edge Exclusion

The edge of an 8-inch SiC wafer deserves more attention than many RFQs give it.

Potential problems include:

• edge chips,
• cracks,
• bevel damage,
• edge roll-off,
• scratches,
• particles,
• polishing irregularities.

These defects can influence:

• robotic handling,
• wafer breakage,
• particle generation,
• coating uniformity,
• usable wafer area.

Request the supplier’s definition of:

edge exclusion

and verify whether defect specifications apply to:

• the full wafer,
• the usable area only,
• or a reduced inspection area.

Otherwise, two defect reports may not be directly comparable.

12. Bare-Substrate Qualification Should Include Epitaxial Results

A polished SiC substrate ultimately needs to perform during epitaxial growth.

Therefore, one of the strongest ways to evaluate a substrate supplier is to examine the substrate’s downstream epi performance.

This does not mean every substrate supplier must operate its own epitaxy line.

But qualification should answer:

How does this substrate behave after epitaxy?

Important parameters can include:

• epitaxial thickness,
• thickness uniformity,
• net doping concentration,
• doping uniformity,
• surface morphology,
• triangular defects,
• carrots,
• downfall defects,
• particles,
• epi-generated stacking faults,
• BPD conversion behavior.

A substrate that looks acceptable before epitaxy may reveal hidden problems after high-temperature epi processing.

13. For Epi Wafers, Require Separate Substrate and Epi Specifications

If purchasing a 200 mm SiC epitaxial wafer, do not accept a specification that only describes the epitaxial layer.

You need both:

Substrate specification

• polytype,
• orientation,
• resistivity,
• thickness,
• TTV,
• bow,
• warp,
• crystal defects,
• backside condition.

Epitaxial specification

• epi thickness,
• thickness uniformity,
• doping target,
• doping uniformity,
• surface defect density,
• BPD-related requirements,
• morphology,
• particle control.

This makes it easier to determine whether a problem originated in the substrate or the epitaxial process.

14. The CoA Should Contain Actual Data

A Certificate of Analysis — CoA is an important part of SiC wafer procurement.

However, not all CoAs provide the same information.

A weak CoA may simply state:

Diameter: PASS
Thickness: PASS
TTV: PASS
Bow: PASS
Warp: PASS

A better CoA reports actual values.

For example:

Diameter: 200.xxx mm
Thickness: xxx.x µm
TTV: x.x µm
Bow: x.x µm
Warp: xx.x µm
Resistivity: xx.x mΩ·cm

For important production lots, actual values are generally more useful than simple pass/fail statements.

15. What Should a Good SiC Wafer CoA Include?

Depending on the agreed specification, a useful CoA may include:

Identification

• customer PO,
• supplier lot number,
• boule number,
• wafer ID,
• production date.

Crystal properties

• polytype,
• conductivity type,
• dopant,
• orientation,
• off-cut.

Electrical properties

• resistivity,
• resistivity uniformity if specified.

Geometry

• diameter,
• thickness,
• TTV,
• bow,
• warp.

Surface

• polishing condition,
• roughness,
• particles,
• scratches.

Crystal defects

• micropipes,
• BPD,
• TSD,
• TED,
• other agreed defect classes.

Epitaxy, where applicable

• epi thickness,
• doping,
• uniformity,
• epi defect density.

The exact CoA does not need to be identical for every application.

It should match the parameters that matter to the customer’s process.

16. Lot Traceability Is Becoming Increasingly Important

For R&D orders involving one or two wafers, traceability may appear secondary.

For qualification and production, it is critical.

A good traceability system should allow a wafer to be linked back through:

Wafer ID → Lot → Boule → Crystal Growth → Slicing → Grinding → CMP → Inspection → Packaging

For epitaxial wafers, the chain may continue through:

Epitaxy Run → Reactor → Process Recipe → Inspection

The purpose is not paperwork for its own sake.

Traceability allows both customer and supplier to investigate problems.

For example, if several wafers show abnormal warp, traceability can help determine whether they originated from:

• the same boule,
• the same slicing batch,
• the same polishing run,
• or the same epi reactor run.

Without traceability, root-cause analysis becomes much harder.

17. Ask Whether Wafer IDs Are Permanent and Unique

For production qualification, each wafer should ideally have a unique identifier.

Buyers should confirm:

• marking method,
• marking location,
• orientation relative to notch,
• whether the ID survives processing,
• whether the ID matches the CoA,
• whether electronic records can be retrieved later.

A CoA without a reliable connection to the physical wafer has limited value.

18. Evaluate Lot-to-Lot Consistency

The qualification mistake buyers most frequently need to avoid is approving a supplier based on one exceptional sample lot.

Instead, qualification should preferably include multiple lots.

Compare:

• Lot A,
• Lot B,
• Lot C.

Look for trends in:

• TTV,
• bow,
• warp,
• resistivity,
• defects,
• polishing quality,
• epi performance.

The objective is not to find a supplier capable of making one excellent wafer.

The objective is to find a supplier capable of reproducing the required quality repeatedly.

19. Ask About Crystal-to-Wafer Mapping

For advanced qualification programs, it may be useful to understand where each wafer originated within the boule.

Crystal characteristics can vary along the growth direction.

Therefore, ask whether the supplier records information such as:

• boule ID,
• wafer sequence,
• axial location,
• growth sector,
• defect distribution.

This information can become valuable during long-term device-yield analysis.

20. Review Packaging and Shipping

A perfectly manufactured 200 mm SiC wafer can still be damaged during packaging or transportation.

Supplier qualification should therefore include the packaging process.

Check:

• individual wafer protection,
• wafer cassette or box compatibility,
• cleanroom packaging,
• vacuum or inert packaging where required,
• shock protection,
• humidity control if relevant,
• outer carton protection,
• labeling,
• wafer orientation.

After receipt, inspect for:

• edge chips,
• particles,
• box damage,
• wafer movement,
• broken packaging seals.

Incoming inspection should separate manufacturing defects from transportation damage.

21. Request an Incoming Inspection Agreement

Before volume purchasing, both buyer and supplier should agree on how incoming inspection will be performed.

The agreement may define:

• inspection equipment,
• measurement method,
• sampling rate,
• acceptance criteria,
• edge exclusion,
• measurement locations,
• dispute procedure.

This is particularly important for parameters where different instruments can produce slightly different results.

Examples include:

• bow,
• warp,
• roughness,
• particle counts,
• defect classification.

The measurement method should ideally be agreed before a rejection occurs.

22. Check Change-Control Procedures

A supplier may qualify successfully and later change:

• crystal-growth conditions,
• raw material,
• polishing slurry,
• CMP equipment,
• inspection equipment,
• epitaxy reactor,
• cleaning chemistry,
• packaging.

Some changes may affect wafer performance even if the nominal specification remains unchanged.

Production customers should therefore discuss a PCN — Process Change Notification procedure.

The supplier should clarify which process changes require:

• customer notification,
• requalification,
• sample approval,
• updated documentation.

This becomes increasingly important as 200 mm SiC moves toward higher-volume manufacturing.

23. Supplier Qualification Checklist for 8-Inch SiC

A practical qualification checklist can include:

Technical Capability

• Can the supplier repeatedly manufacture true 200 mm SiC?
• What grades are available?
• Is the wafer Si-face CMP?
• Can the required resistivity be controlled?
• Are TTV, bow and warp measured wafer by wafer?

Defect Control

• Which crystal defects are measured?
• Is a defect map available?
• What inspection equipment is used?
• Is edge exclusion clearly defined?
• Are actual values available?

Epitaxial Quality

• Is epi performance data available?
• Can epi thickness uniformity be reported?
• Can doping uniformity be reported?
• Are epi surface defects classified?

Documentation

• Is a CoA supplied?
• Does it contain actual values?
• Is each wafer uniquely identified?
• Can the wafer be traced to the boule?

Production Stability

• Can multiple lots be compared?
• Is SPC data available where appropriate?
• Are specification distributions stable?
• Is there a process-change notification procedure?

Logistics

• Is semiconductor-grade packaging used?
• Is the wafer protected from edge damage?
• Can lot and wafer IDs be verified at receipt?

24. Sample RFQ Structure for a 200mm SiC Substrate

A practical RFQ may look like this:

Product: 200 mm 4H-SiC Substrate
Conductivity: N-Type
Dopant: Nitrogen
Orientation: 4° off-axis toward agreed direction
Diameter: 200 mm with agreed tolerance
Thickness: Customer-defined
Resistivity: Customer-defined range
Surface: Si-face CMP, epi-ready
Backside: Customer-defined
TTV: Customer-defined maximum
Bow: Customer-defined maximum
Warp: Customer-defined maximum
Si-face roughness: Customer-defined Ra and AFM condition
Crystal defects: MP/BPD/TSD/TED limits as required
Surface defects: Defined scratches, particles, pits and chips
Edge: Defined bevel and edge exclusion
Inspection: Defect map requested
Documentation: CoA with actual measurement data
Traceability: Wafer ID + lot ID + boule ID
Quantity: Samples / qualification lot / production quantity
Application: MOSFET / Schottky diode / epitaxy / process development

Providing this information early usually produces a much more meaningful quotation than simply requesting:

Please quote 8-inch SiC wafers.

25. Price Should Be Compared Against Qualified Yield

For 200 mm SiC, the lowest unit price is not always the lowest manufacturing cost.

Imagine:

Supplier A: lower wafer price but wider geometry distribution and higher defect variability.

Supplier B: higher wafer price but better lot consistency and higher downstream device yield.

The correct comparison is not necessarily:

USD per wafer

but increasingly:

Cost per usable wafer

or even:

Cost per qualified device area.

This distinction becomes more important as wafer diameter and wafer value increase.

26. Red Flags When Evaluating an 8-Inch SiC Supplier

Buyers should investigate further if a supplier:

• provides only generic specifications,
• cannot provide actual TTV/bow/warp data,
• cannot explain its defect inspection method,
• provides no wafer IDs,
• cannot link wafers to production lots,
• cannot explain edge exclusion,
• provides only a generic CoA,
• refuses to discuss lot-to-lot variation,
• cannot distinguish typical and guaranteed values,
• cannot provide evidence of 200 mm processing,
• describes everything simply as “epi-ready.”

None of these points alone automatically proves that a supplier is unsuitable.

But they are reasons to request additional evidence before production qualification.

27. Why Supplier Qualification Matters More in 2026

The SiC industry is gradually moving from a predominantly 150 mm manufacturing environment toward broader 200 mm adoption.

That transition is not simply about increasing wafer diameter.

It requires the entire manufacturing chain to demonstrate:

• larger crystal capability,
• lower defect density,
• better wafer geometry,
• stable polishing,
• reliable epitaxy,
• automated handling,
• advanced inspection,
• stronger traceability.

As 8-inch SiC processes move closer to volume manufacturing, substrate suppliers will increasingly be evaluated not only on whether they can manufacture a 200 mm wafer, but on whether they can support production-level quality systems.

Conclusion

Qualifying an 8-inch SiC wafer supplier requires much more than comparing diameter, thickness and price.

A strong qualification program should evaluate the entire quality chain:

Crystal quality → Defect mapping → TTV/Bow/Warp → Surface quality → Epitaxy → CoA → Wafer ID → Lot traceability → Packaging → Lot-to-lot consistency

The most important principle is simple:

Do not qualify the specification sheet. Qualify the manufacturing process behind the specification sheet.

For R&D applications, a few passing wafers may be sufficient.

For production applications, buyers need evidence that the supplier can consistently reproduce the same quality across wafers, lots and time.

As 200 mm SiC adoption expands, defect maps, actual measurement data, CoA documentation and complete lot traceability will increasingly separate a sample supplier from a production-capable SiC wafer partner.

FAQ

What information should I request before buying an 8-inch SiC wafer?

At minimum, request polytype, conductivity type, orientation, off-cut, thickness, resistivity, TTV, bow, warp, surface finish, roughness, crystal-defect specifications, edge quality and a CoA. For qualification programs, also request defect maps and wafer-level traceability.

Is a CoA enough to qualify a SiC wafer supplier?

Not by itself. A CoA is useful, but buyers should determine whether it contains actual measurement values or only pass/fail statements. Production qualification should also evaluate defect maps, inspection methods, traceability and lot-to-lot consistency.

Why are TTV, bow and warp especially important for 200mm SiC?

As wafer diameter increases, wafer shape has greater influence on chucking, robotic handling, epitaxy, lithography and downstream processing. TTV, bow and warp measure different aspects of wafer geometry and should therefore be specified and evaluated separately.

Should I request a defect map for every wafer?

That depends on the application, price level and qualification stage. For initial supplier qualification, high-voltage device development or critical production lots, defect maps can provide valuable information that average defect-density numbers cannot show.

What is the difference between a good sample supplier and a production-qualified supplier?

A sample supplier may be able to provide several wafers that meet specification. A production-qualified supplier should demonstrate repeatable quality across multiple wafers and multiple lots, with controlled inspection methods, CoA data, unique wafer identification, process traceability and change control.

What should be included in SiC wafer lot traceability?

Ideally, the supplier should be able to connect each wafer ID to its production lot and boule, and maintain records covering crystal growth, slicing, grinding, polishing, inspection and packaging. For epitaxial wafers, epi-run information should also be traceable.