Silicon carbide (SiC) has emerged as a critical material in high-performance power semiconductor devices due to its wide bandgap, high thermal conductivity, high breakdown field, and high electron drift velocity. These properties make SiC power devices ideal for electric vehicles, energy storage systems, and renewable energy inverters, offering lower conduction losses and higher efficiency compared to traditional silicon devices. This article provides a detailed, technical overview of SiC power device fabrication, focusing on substrates, epitaxial growth, doping control, defect management, and current trends in the industry.
1. Core Material: 4H-SiC Single Crystal Substrate
4H-SiC is the most commonly used polytype in power device manufacturing. The “4H” denotes a stacking sequence along the c-axis in which four Si-C bilayers form one hexagonal unit cell (ABCB stacking). Key material advantages include:
| Property | Value | Significance |
|---|---|---|
| Bandgap | ~3.3 eV | High-temperature operation |
| Critical Breakdown Field | 2–3 MV/cm | High-voltage tolerance |
| Thermal Conductivity | ~4.9 W/cm·K | Efficient heat dissipation |
| Electron Drift Velocity | ~2×10⁷ cm/s | Suitable for high-frequency operation |
These properties make 4H-SiC ideal for manufacturing high-voltage, high-current, high-temperature, and high-frequency devices.
2. Substrate Orientation and Off-Axis Design
SiC {0001} crystal planes can be classified as:
- Si-face (0001): Topmost atoms are silicon. Surface properties favor controlled epitaxial growth and low defect densities.
- C-face (000-1): Topmost atoms are carbon. High chemical activity leads to faster growth but increased defect formation and more challenging doping control.
Commercial power devices almost exclusively use Si-face off-axis substrates, typically tilted 3.5°–4° toward the <11-20> direction. This creates atomic steps that support step-flow growth, suppress two-dimensional nucleation, reduce defects, and yield atomically flat epitaxial layers.
3. SiC Epitaxial Growth Process
Epitaxial growth is the deposition of a single-crystal SiC layer on a single-crystal substrate, maintaining the same crystal structure. It forms the active regions of devices such as MOSFET drift layers and P+ layers. The standard method is Chemical Vapor Deposition (CVD).
3.1 Substrate Preparation
| Step | Purpose | Typical Parameters |
|---|---|---|
| Hydrogen Etching | Remove scratches, native oxide, contamination, form atomic steps | 1500–1650°C, several minutes |
| Cleaning | Remove particles and metal ions | RCA clean (SC1, SC2, DHF) |
3.2 Epitaxial Growth Parameters
| Parameter | Typical Range | Notes |
|---|---|---|
| Temperature | 1500–1650°C | High temperature promotes precursor decomposition and atomic surface diffusion |
| Pressure | 100–300 mbar | Low pressure improves thickness uniformity and reduces particle formation |
| Silicon Source | SiH₄ or SiH₂Cl₂ | SiH₂Cl₂ preferred to suppress 3C-SiC polytype and triangular defects |
| Carbon Source | C₃H₈ (Propane) or C₂H₄ (Ethylene) | Propane most common; ethylene used for low-temperature growth or improved uniformity |
| Si/C Ratio | 0.7–1.0 | Slightly C-rich to avoid Si droplets and polytype inclusions |
| Doping (N-type) | N₂ or NH₃ | NH₃ offers higher efficiency and less precursor required |
| Doping (P-type) | TMA or TEA | Low efficiency, requires precise control to prevent Al-C complex formation |
| Growth Rate | 5–20 µm/h | Balances production efficiency and defect control |
| Step-Flow Growth | Achieved via off-axis substrate and controlled temperature, pressure, Si/C ratio | Suppresses 2D nucleation, reduces defects, ensures atomic flatness |
During growth, adatoms preferentially incorporate at step edges, and steps propagate across terraces, forming a smooth, low-defect epitaxial layer.
3.3 Cooling and Unloading
After growth, wafers are cooled under H₂ or inert gas to prevent thermal stress and wafer cracking. Only after reaching safe temperatures are wafers removed from the reactor.
4. Defect Types and Challenges
SiC epitaxy faces several critical challenges in defect control:
| Defect Type | Cause | Impact on Device |
|---|---|---|
| Triangular defects | Substrate particles, scratches, 3C-SiC inclusions | Reduces yield and reliability |
| Carrot defects | Carbon inclusions or substrate defects | Surface roughness, localized defects |
| Polytype inclusion | 3C-SiC grains | Disrupts single crystal integrity |
| Substrate inherited defects | Basal plane dislocations (BPD), threading edge dislocations (TED) | BPD can convert to stacking faults under high fields, increasing on-resistance |
Optimized step-flow growth and careful substrate preparation can partially block BPD propagation and reduce their impact.
5. Industry Trends
- Larger Wafer Sizes: Transitioning from 100 mm to 150 mm and 200 mm wafers to improve single-crystal utilization.
- Lower Defect Density: Optimizing temperature, pressure, Si/C ratio, and precursor choice to minimize BPDs and triangular defects.
- Improved Doping Control: Especially for P-type doping to achieve uniformity and efficiency.
- High Growth Rate: Exploring >30 µm/h growth while maintaining quality using advanced precursors like SiHCl₃ (TCS).
- In-situ Monitoring: Laser interferometry, optical pyrometry, and ellipsometry to monitor growth in real time.
- Multi-layer Structures: Precise epitaxy of N+/N-/P-well/N+ layers for complex devices like MOSFETs and IGBTs.
6. Conclusion
SiC epitaxial growth on 4H-SiC Si-face off-axis substrates forms the foundation for high-performance power devices. Mastery of substrate orientation, off-axis design, step-flow growth, and precise control of CVD parameters is essential to achieve low-defect, uniform, and high-quality epitaxial layers. Ongoing advances in wafer size, growth rate, defect control, and in-situ monitoring will continue to drive SiC devices toward higher performance, lower cost, and broader applications in energy-efficient electronics.